GWIXP425BDT datasheet(100/134 Pages) INTEL

100 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

100

Document Number: 252479, Revision: 005

5.5.2.6

SDRAM Bus

Figure 24.

SDRAM Input Timings

Table 51.

SDRAM Input Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tsetup

Input setup prior to rising edge of clock. Inputs

included in this timing are SDM_DQ[31:0] (during

a read operation).

1.4

Thold

Input hold time after the rising edge of the clock.

Inputs included in this timing are SDM_DQ[31:0]

(during a read operation).

1.5

Figure 25.

SDRAM Output Timings

Table 52.

SDRAM Output Timings Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tclk2out

Rising edge of clock-to-signal output. Outputs

included in this timing are SDM_ADDR[12:0],

SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE,

SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N,

SDM_RAS_N, SDM_DQ[31:0] (during a write

operation).

5.5

Tholdout

Signal output hold time after the rising edge of

the clock. Outputs included in this timing are

SDM_DQ[31:0] (during a write operation).

1.5

Note:

Timing test were performed with a 70-pF load to ground.

B4891-01

Tsetup

Thold

Clock

Signals

A9584-01

Tclk2out

Tholdout

Data Valid

Clock

Signals

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