M16CSLASH62P datasheet(55/87 Pages) RENESAS

55 / 87 page

VCC1 = VCC2 = 3V

M16C/62 Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics (M16C/62P)

page 55

Timing Requirements

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 5.33 Memory Expansion and Microprocessor Modes

Table 5.32 External Clock Input (XIN input)

Max.

External clock rise time

Min.

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock fall time

tw(H)

tw(L)

Parameter

Symbol

Unit

Standard

100

(Note 1)

(Note 2)

(Note 3)

1. Calculated according to the BCLK frequency as follows:

Min.

Data input setup time

tsu(DB-RD)

tsu(RDY-BCLK )

Parameter

Symbol

Unit

Max.

Standard

RDY input setup time

Data input hold time

th(RD-DB)

th(BCLK -RDY)

RDY input hold time

HOLD input setup time

tsu(HOLD-BCLK )

HOLD input hold time

th(BCLK-HOLD )

Data input access time (for setting with no wait)

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

Data input access time (for setting with wait)

Data input access time (when accessing multiplex bus area)

f(BCLK)

– 60

0.5 X 109

[ns]

2. Calculated according to the BCLK frequency as follows:

f(BCLK)

– 60

(n–0.5) X 109

[ns]

3. Calculated according to the BCLK frequency as follows:

f(BCLK)

– 60

(n–0.5) X 109

[ns]

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait

setting.

n is “2” for 2-wait setting, “3” for 3-wait setting.

NOTES:

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