18

µµµµPC1857A

3.2.1 1-byte data transfer

The format in which 1-byte data is to be transferred is as follows:

Start Slave address

Subaddress

Data

Stop

Write

mode

ACK

ACK

ACK

3.2.2 Successive data transfer

The

µPC1857A has an automatic increment function which can be used to transfer successive data (refer to 4.4.6

Automatic increment).

By using this function, the internal subaddress is automatically incremented if a slave address and a subaddress

have been set, so that the data from subsequent subaddresses can be transferred in succession.

Incrementing the subaddress of the

µPC1857A is stopped when the subaddress reaches “04H”.

The format in which 5 bytes of data are to be transferred in succession by using the automatic increment function

is as follows:

Start Slave address

Subaddress

Data 1

Write

mode

Data 2

Data 5

Stop

ACK

ACK

ACK

ACK

ACK

The host CPU transfers “00H” as subaddress SA0 after start and slave addresses, as shown above. Data SA0 is

transferred after this subaddress SA0, and without transferring the stop condition the data SA1, SA2, SA3, and SA4 are

transferred successively, and then the stop condition is transferred.

To successively change data at a fixed subaddress, for example to turn up/down the volume, turn off the

automatic increment function.

3.2.3 Acknowledge

On the I

2C bus, an acknowledge bit is appended to the 9th bit following the data. This acknowledge bit is used to

judge whether data transfer has been successful. The host CPU judges whether data transfer has been successful

or not, depending on whether the status of the acknowledge bit is “H” or “L”.

When the acknowledge bit is “L”, it indicates success. When the acknowledge bit is “H”, it indicates failure of

transfer or forced release of bus (NAK status). The NAK status occurs when a wrong slave address is transferred to

a slave IC or data transfer from slave side is finished in the read status.