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74ALVT162821 데이터시트(PDF) 10 Page - Nexperia B.V. All rights reserved |
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74ALVT162821 데이터시트(HTML) 10 Page - Nexperia B.V. All rights reserved |
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10 / 15 page ![]() Nexperia 74ALVT162821 20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state 001aal795 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled nQn output LOW-to-OFF OFF-to-LOW nQn output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM VM GND GND tPZL tPZH VM VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays Table 8. Measurement points Input Output VCC VI VM VM VX VY VCC ≤ 2.7 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V VCC ≥ 3.0 V 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVT162821 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 19 October 2020 10 / 15 |
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