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CS5535 데이터시트(PDF) 419 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 CS5535
상세설명  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
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CS5535 데이터시트(HTML) 419 Page - National Semiconductor (TI)

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LPC Port Register Descriptions (Continued)
5.14.1 LPC Specific MSRs
The LPC Controller uses the MSR_LPC_EADDR and MSR_LPC_ESTAT to record the indicated information associated
with any given LPC bus error. The recorded information can not be cleared or modified. Simultaneous with this recording,
an error event is sent to the DIVIL GLD_MSR_ERROR (MSR 51400003h). If enabled at the DIVIL GLD_MSR_ERROR, any
LPC error event is recorded with a flag. This flag can be cleared. The status of this flag should be used to determine if there
is an outstanding error associated with the two MSRs below.
5.14.1.1
LPC Address Error (LPC_EADDR)
5.14.1.2
LPC Error Status (LPC_ESTAT)
MSR Address
5140004Ch
Type
RO
Reset Value
00000000h
LPC_EADDR Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
LPC_ERR_ADDR
LPC_EADDR Bit Descriptions
Bit
Name
Description
31:0
LPC_ERR_ADDR
LPC Error Address. When an error occurs, this register captures the associated 32-bit
address.
MSR Address
5140004Dh
Type
RO
Reset Value
00000000h
LPC_ESTAT Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RSVD
ESTAT Bit Descriptions
Bit
Name
Description
31:4
RSVD
Reserved. Reads as 0.
3TIMEOUT
Timeout. If set, indicates an LPC error was caused by a timeout.
2DMA
DMA. If set, indicates an LPC error occurred during a DMA transaction.
1WRITE
Write. If set, indicates an LPC error occurred during an LPC write transaction.
0MEMORY
Memory. If set, indicates an LPC error occurred during an LPC memory transaction.



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