CS5535 datasheet(420/555 Pages) NSC

420 / 555 page

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420

Revision 0.8

LPC Port Register Descriptions (Continued)

5.14.1.3

LPC Serial IRQ Control (LPC_SIRQ)

5.14.1.4

LPC Reserved (LPC_RSVD)

MSR Address

5140004Eh

Type

R/W

Reset Value

00000000h

LPC_SIRQ Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

INVERT[15:0]

RSVD

IRQ_FRAME

START

_FPW

LPC_SIRQ Bit Descriptions

Bit

Name

Description

31:16

INVERT[15:0]

Invert bits 15 through 0. Each invert[x] bit corresponds to an irq[x] bit. When a given x

bit is 1, the corresponding serial IRQ input is assumed active low. Active low inputs are

inverted and presented internally as active high inputs.

15:8

RSVD

Reserved. Write as 0.

SIRQ_EN

Serial IRQ Enable. 0: Disable; 1: Enable

SIRQ_MODE

Serial IRQ Interface Mode. 0: Continuous (Idle); 1: Quiet (Active)

5:2

IRQ_FRAME

IRQ Data Frames. Number of frames.

0000: 17.

0100: 21.

1000: 25.

1100: 29.

0001: 18.

0101: 22.

1001: 26 .

1101: 30.

0010: 19.

0110: 23.

1010: 27.

1110: 31.

0011: 20.

0111: 24.

1011: 28.

1111: 32.

1:0

START_FPW

Start Frame Pulse Width. Sets the start frame pulse width, specified by the number of

clocks.

00: 4 clocks.

10: 8 clocks.

01: 6 clocks.

11: Reserved.

MSR Address

5140004Fh

Type

R/W

Reset Value

00000000h

LPC_RSVD Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

RSVD

LPC_RSVD Bit Descriptions

Bit

Name

Description

31:0

RSVD

Reserved. Reads return 0. Writes have no effect.

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