CS5535 datasheet(551/555 Pages) NSC

551 / 555 page

Revision 0.8

551

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Electrical Specifications (Continued)

6.4

POWER SUPPLY SEQUENCE REQUIREMENTS

The voltages applied to the CS5535 are subject to the

requirements listed below as well as the requirements of

Table 6-3 "Recommended Operating Conditions" on page

526. Reference values “minimum” and “maximum” below

should be taken from Table 6-3.

Note that the information below is provided for complete-

ness. Since the specified margins are very wide, the typical

power supply implementation meets them without problem.

If these requirements are not observed, the RTC circuit

and/or the LVD circuit may not operate correctly.

VCORE and VIO may come up in any order but must

meet their respective minimum values within 100 ms of

each other.

From zero volts, VCORE and VIO must ramp up mono-

tonically and reach 90% of their respective minimum

values no sooner that 10 µs and no later than 1 sec-

ond.

From their respective minimum values, VCORE and VIO

must ramp down to within 0.4 volts of ground no

sooner than 100 ms and no later than 5 seconds.

Same as requirement 1, but for VCORE_VSB and

VIO_VSB.

Same

requirement

but

for

VCORE_VSB

(VDD_VSB) and VIO_VSB.

Same as requirement 3 but for VCORE_VSB and

VIO_VSB.

The absolute value of the delta between VCORE and

VCORE_VSB must not exceed 0.25 volts.

The absolute value of the delta between VIO and

VIO_VSB must not exceed 0.25 volts.

CS5535 데이터시트(PDF) 551 Page - National Semiconductor (TI)