CS5535 datasheet(552/555 Pages) NSC

552 / 555 page

www.national.com

552

Revision 0.8

Electrical Specifications (Continued)

6.5

LOW VOLTAGE DETECT (LVD) PARAMETERS

The LVD electrical parameters are defined in Figure 6-11

and

listed

Table

6-24.

Use

internal

signals

power_good_standby and power_good_working is illus-

trated in Figure 3-6 "Reset Logic" on page 59.

In this subsection, unless otherwise noted:

• All timing specifications are specified under the oper-

ating conditions listed in Table 6-3 on page 526 (i.e.,

VCORE (VDD) and VCORE_VSB (VDD_VSB) = All; VIO

(VDDIO) and VIO_VSB (VDDIO_VSB) = All; TCASE = All).

• The LVD circuit incorporates no clock signals.

Figure 6-11. LVD Electrical Parameter Definitions

Table 6-24. LVD Parameters

Signal

Parameter

Min

Max

Units

Comment/Condition

power_good_standby

VRASING_TRIP_CORE_VSB

0.90

1.00

VFALLING_TRIP_CORE_VSB

0.72

0.90

VHYSTERESIS_CORE_VSB

110

Note 1.

VRASING_TRIP_IO_VSB

2.15

2.85

VFALLING_TRIP_IO_VSB

2.32

2.80

VHYSTERESIS_IO_VSB

100

580

Note 1.

power_good_working

VRASING_TRIP_CORE

0.90

1.00

VFALLING_TRIP_CORE

0.72

0.90

VHYSTERESIS_CORE

110

Note 1.

Note 3:

Note 1. The resulting circuit has high noise immunity. Any glitches less than 150 ns are rejected. Hysteresis is guaranteed

by design.

V = VOPERATING

V = VRAISING_TRIP

V = VFALLING_TRIP

V = 0

power_good ~=

VCORE_VSB

power_good ~= VSS

CS5535 데이터시트(PDF) 552 Page - National Semiconductor (TI)

CS5535 데이터시트(HTML) 552 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL