UPD6P9 datasheet(32/45 Pages) RENESAS

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µPD6P9

Data Sheet U15144EJ1V1DS

AC programming characteristics (TA = 25

°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Address setup timeNote 1 (to MD0

↓)tAS

µs

MD1 setup time (to MD0

↓)tM1S

µs

Data setup time (to MD0

↓)tDS

µs

Address hold timeNote 1 (from MD0

↑)tAH

µs

Data hold time (from MD0

↑)tDH

µs

Delay time from MD0

↑ to data output float

tDF

130

VPP setup time (to MD3

↑)tVPS

µs

VDD setup time (to MD3

↑)tVDS

µs

Initial program pulse width

tPW

0.95

1.0

1.05

Additional program pulse width

tOPW

0.95

21.0

MD0 setup time (to MD1

↑)tMOS

µs

Delay time from MD0

↓ to data output

tDV

MD0 = MD1 = VIL

µs

MD1 hold time (from MD0

↑)tM1H

tM1H+tM1R

≥ 50

µs2

µs

MD1 recovery time (to MD0

↓)tM1R

µs

Program counter reset time

tPCR

µs

CLK input high-/low-level width

tXH, tXL

0.125

µs

CLK input frequency

4.19

MHz

Initial mode set time

µs

MD3 setup time (to MD1

↑)tM3S

µs

MD3 hold time (from MD1

↓)tM3H

µs

MD3 setup time (to MD0

↓)tM3SR

When program memory is read

µs

Delay time from addressNote 1 to data output

tOAD

When program memory is read

µs

Hold time from addressNote 1 to data output

tHAD

When program memory is read

130

MD3 hold time (from MD0

↑)tM3HR

When program memory is read

µs

Delay time from MD3

↓ to data output float

tDFR

When program memory is read

µs

Reset setup time

tRES

µs

Oscillation stabilization wait timeNote 2

tWAIT

2ms

Notes 1. The internal address signal is incremented at the falling edge of the third clock of CLK.

2. Connect a 4 MHz ceramic resonator between the XIN and XOUT pins.

UPD6P9 데이터시트(PDF) 32 Page - Renesas Technology Corp

UPD6P9 데이터시트(HTML) 32 Page - Renesas Technology Corp

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