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DS20005604D-page 5

MIC4606

Upper Turn-On Propagation

Delay (xHI Rising to xHO

Rising)

tHPLH

—35

75

ns

Output Rise/Fall Time

tR/tF

—20

—

ns

CL = 1000 pF

Output Rise/Fall Time

(3V to 9V)

tR/tF

—0.8

—

µs

CL = 0.1 µF

Minimum Input Pulse Width

that Changes the Output

tPW

—50

—

ns

Switching Specifications (Note 5)

Delay from xPWM High (or

xLI Low) to xLO Low

tLOOFF

—35

75

ns

xLO Output Voltage

Threshold for Low-Side FET

to be Considered Off

VLOOFF

—1.9

—

V

Delay from xLO Off to xHO

High

tHOON

—35

75

ns

Delay from xPWM Low (or

xHI Low) to xHO Low

tHOOFF

—35

75

ns

Switch Node Voltage

Threshold Signaling xHO is

Off

VSWTH

12.2

4

V

Delay Between xHO FET

being Considered Off to xLO

Turning On

tLOON

—35

75

ns

For xHS Low/xLI High, Delay

from xPWM/xHI Low to xLO

High

tLOONHI

—80

150

ns

Force xLO On if VSWTH is

Not Detected

tSWTO

100

250

500

ns

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics:

Unless otherwise indicated: VDD = VxHB = 12V; VEN = 5V; VSS = VxHS = 0V; No load on

xLO or xHO; TA = +25°C. Bold values indicate -40°C ≤ TJ ≤ +125°C.(1,2)

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1:

Specification for packaged product only.

2:

“x” in front of a pin name refers to either A or B (e.g., xHI can be either AHI or BHI).

3:

VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic low.

VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic high.

4:

xLI/xHI mode with inputs non-overlapping, assumes xHS low before xLI goes high and xLO low before xHI

goes high.

5:

PWM mode (MIC4606-2) or LI/HI mode (MIC4606-1) with overlapping xLI/xHI inputs.