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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72344 데이터시트(PDF) 63 Page - STMicroelectronics |
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ST72344 데이터시트(HTML) 63 Page - STMicroelectronics |
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63 / 191 page  ST72340, ST72344, ST72345 63/191 WINDOW WATCHDOG (Cont’d) 11.1.9 Interrupts None. 11.1.10 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watch- dog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cy- cles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). WINDOW REGISTER (WDGWR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 = Reserved Bits 6:0 = W[6:0] 7-bit window value These bits contain the window value to be com- pared to the downcounter. 70 WDGA T6 T5 T4 T3 T2 T1 T0 70 -W6 W5 W4 W3 W2 W1 W0 |
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