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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72344 데이터시트(PDF) 104 Page - STMicroelectronics |
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ST72344 데이터시트(HTML) 104 Page - STMicroelectronics |
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104 / 191 page  ST72340, ST72344, ST72345 104/191 When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read oper- ation followed by a SCIDR register read operation. Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram TRANSMITTER RECEIVER SCIETPR SCIERPR EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED PRESCALER CLOCK CLOCK RECEIVER RATE TRANSMITTER RATE SCIBRR SCP1 fCPU CONTROL CONTROL SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 /PR /16 CONVENTIONAL BAUD RATE GENERATOR EXTENDED RECEIVER PRESCALER REGISTER EXTENDED TRANSMITTER PRESCALER REGISTER |
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