STV0672 datasheet(54/105 Pages) STMICROELECTRONICS

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VV5410 & VV6410

Digital Video Interface Format

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The slow QCK, clocks at pixel rate. Both the falling and rising edge of this clock are used to qualify data. The most significant

data nibble is qualified by the rising edge of the slow QCK and the least significant nibble is qualified by the falling edge of

the slow QCK.

There are 4 modes of operation of QCK.

1. Disabled (Always low - default mode of operation)

2. Free running - qualiﬁes the entire output data stream.

3. Qualify embedded control sequences, status data, (from the SOF line), and pixel data.

4. Qualify pixel data only, (this will include data from the black lines).

The operating mode for QCK is set via the serial interface. The QCK output can be tri-stated either when OEB is driven high or

via the appropriate control bit in the serial interface, (see data_format register[22]).

The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor to control

external devices, e.g. stepper motors, shutter mechanisms.

Full details of how to configure the QCK output pin can be found in 2 registers, fg_mode[20] and pin_mapping[21].

STV0672 데이터시트(PDF) 54 Page - STMicroelectronics