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PLUS16R6 데이터시트(PDF) 13 Page - NXP Semiconductors

부품명 PLUS16R6
상세설명  PAL devices
PDF  16 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PLUS16R6 데이터시트(HTML) 13 Page - NXP Semiconductors

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1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
VT
1.5V
1.5V
+3V
0V
+3V
0V
VOH
VOL
+3V
0V
I, B
(INPUTS)
CLK
Q
(REGISTERED OUTPUTS)
OE
tIH
tIS
tIS
tCKH
tCKL
tCKP
tCKO
tOD1
tOE1
Flip-Flop Outputs
I, B
(INPUTS)
O, B
(COMBINATORIAL
OUTPUTS)
I, B
(OUTPUT
ENABLE)
tPD
tOE2
tOD2
1.5V
1.5V
+1.5V
+1.5V
VT
+3V
0V
VOH
VOL
+3V
0V
Gate Outputs
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
0V
VOH
VOL
+3V
0V
+3V
0V
VCC
4.5V
VCC
Q
(REGISTERED
OUTPUTS)
I, B
(INPUTS)
CLK
tPPR
tCKO
tIH
tIS
tIS
tCKH
tCKL
tIS+tCKF
Power–Up Reset
Philips Semiconductors Programmable Logic Devices
Product specification
PLUS16R8D/-7 SERIES
PAL devices
16L8, 16R8, 16R6, 16R4
September 10, 1993
48
TIMING DIAGRAMS1, 2
NOTES:
1. Input pulse amplitude is 0V to 3V.
2. Input rise and fall times are 2.5ns.
TIMING DEFINITIONS
SYMBOL
PARAMETER
tCKH
Width of input clock pulse.
tCKL
Interval between clock pulses.
tCKP
Clock period.
tIS
Required delay between
beginning of valid input and
positive transition of clock.
tIH
Required delay between
positive transition of clock and
end of valid input data.
tCKF
Delay between positive
transition of clock and when
internal Q output of flip-flop
becomes valid.
tCKO
Delay between positive
transition of clock and when
outputs become valid (with
OE Low).
tOE1
Delay between beginning of
Output Enable Low and when
outputs become valid.
tOD1
Delay between beginning of
Output Enable High and when
outputs are in the Off-State.
tOE2
Delay between predefined
Output Enable High, and
when combinational outputs
become valid.
tOD2
Delay between predefined
Output Enable Low and when
combinational outputs are in
the Off-State.
tPPR
Delay between VCC (after
power-on) and when flip-flop
outputs become preset at “1”
(internal Q outputs at “0”).
tPD
Propagation delay between
combinational inputs and
outputs.
FREQUENCY DEFINITIONS
fMAX
No feedback: Determined by
the minimum clock period,
1/(tCKL + tCKH).
Internal feedback:
Determined by the internal
delay from flip-flop outputs
through the internal feedback
and array to the flip-flop
inputs, 1/(tIS + tCKF).
External feedback:
Determined by clock-to-output
delay and input setup time,
1/(tIS + tCKO).



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