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2023 Microchip Technology Inc.

DS20006768B-page 13

ZL40294

FIGURE 3-5:

POWER SUPPLY FILTERING.

3.5

OE# and Output Enables (Control Register)

Each output can be individually enabled or disabled by SMBus control register bits or via OE# pin. The OE# pins are

asynchronous asserted-low signals. The Output Enable bits in the SMBus registers are active high and are set to enable

by default.

OE# pins are mapped to CK[12:5] outputs.

Note that the logic level for assertion or de-assertion is different in software than it is on hardware. This follows hardware

default nomenclature for communication channels (e.g., output is enabled if OE# pin is pulled low) and still maintains

software programming logic (e.g., output is enabled if OE register is true).

Refer to Table 3-1 for the truth table for enabling and disabling outputs via hardware and software. Note that both the

control register bit must be a ‘1’ AND the OE# pin must be a ‘0’ for the output to be active.

3.6

OE# Assertion (Transition from ‘1’ to ‘0’)

All differential outputs that were disabled are to resume normal operation in a glitch free manner. The latency from the

assertion to active outputs is 0 - 10 CK clock periods.

3.7

OE# De-Assertion (Transition from ‘0’ to ‘1’)

The impact of de-asserting OE# is each corresponding output will transition from normal operation to disabled in a glitch

free manner. A minimum of four valid clocks will be provided after the de-assertion of OE#. The maximum latency from

the de-assertion to disabled outputs is 10 CK clock periods.

TABLE 3-1:

OE FUNCTIONALITY

Inputs

OE# Hardware Pins and Control Register Bits

PWRGD/

PWRDN#

CK_IN/

CK_IN#

SMBUS

Enable Bit

OE# Pin

CK/CK#

[12:5]

CK/CK#

[4:0] and [19:13]

0

X

X

X

0

0

1

Running

0

X

0

0

1

0

Running

Running

1

1

0

Running