F8NK100Z datasheet(4/13 Pages) STMICROELECTRONICS

4 / 13 page

2 Electrical characteristics

STF8NK100Z - STP8NK100Z

4/13

Table 6.

Switching times

Table 7.

Source drain diode

Table 8.

Gate-source zener diode

(1) Limited only by maximum temperature allowed

(2)ISD ≤ 6.5 A, di/dt ≤ 200A/µs, VDS ≤ V(BR)DSS, Tj≤ Tjmax

(3) Pulse width limited by safe operating area

(4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device’s ESD capability, but

also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to

protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

(5) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0

to 80% VDSS

(6) Pulsed: pulse duartion = 300µs, duty cycle 1.5%

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

td(on)

Turn-on Delay Time

Rise Time

VDD=500 V, ID= 3.15 A,

RG=4.7Ω, VGS=10V

(see Figure 18)

td(off)

Turn-off Delay Time

FallTime

VDD=500 V, ID=3.15 A,

RG=4.7Ω, VGS=10V

(see Figure 18)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

ISD

ISDM Note 3

Source-drain Current

Source-drain Current (pulsed)

6.5

VSDNote 2

Forward on Voltage

ISD=6.3A, VGS=0

1.6

trr

Qrr

IRRM

Reverse Recovery Time

Reverse Recovery Charge

Reverse Recovery Current

ISD=6.3A, di/dt = 100A/µs,

VDD=50 V, Tj=25°C

620

5.3

µC

trr

Qrr

IRRM

Reverse Recovery Time

Reverse Recovery Charge

Reverse Recovery Current

ISD=6.3A, di/dt = 100A/µs,

VDD=50 V, Tj=150°C

840

7.5

µC

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

BVGSO

Note 4

Gate-Source Breakdown

Voltage

Igs = ± 1mA (Open Drain)

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