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High Speed CMOS Logic – 54HC175

Rev 1.0

21/11/17

AC Electrical Characteristics5

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0

0.1

0.1

0.1

4.5

0.1

0.1

0.1

6.0

VIN = VIH or VIL

│IOUT│≤ 20µA

0.1

0.1

0.1

V

4.5

VIN = VIH or VIL

│IOUT│≤ 4.0mA

0.26

0.33

0.4

Maximum Low-Level

Output Voltage

VOL

6.0

VIN = VIH or VIL

│IOUT│≤ 5.2mA

0.26

0.33

0.4

V

Maximum Input

Leakage Current

IIN

6.0

VIN = GND or VCC

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

ICC

6.0

VIN = GND or VDD

IOUT = 0µA

8

80

160

µA

DC Electrical Characteristics Continued (Voltages referenced to GND)

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0

6.0

4.8

4.0

4.5

30

24

20

Maximum Clock

Frequency

(Figure 1, 4)

fmax

6.0

CL = 50pF,

tr = tf = 6ns

35

28

24

MHz

2.0

150

190

225

4.5

30

38

45

Propagation Delay,

Clock to Q or Q

(Figure 1, 4)

tPLH, tPHL

6.0

CL = 50pF,

tr = tf = 6ns

26

33

38

ns

2.0

125

155

190

4.5

25

31

38

Propagation Delay,

Reset to Q or Q

(Figure 2, 4)

tPLH, tPHL

6.0

CL = 50pF,

tr = tf = 6ns

21

26

32

ns

2.0

75

95

110

4.5

15

19

22

Output Transition

Time, Any Output

(Figure 1, 4)

tTLH, tTHL

6.0

CL = 50pF,

tr = tf = 6ns

13

16

19

ns

Input Capacitance

CIN

-

CL = 50pF,

tr = tf = 6ns

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance

(Per Flip-Flop)

CPD

-

TJ = 25°C,

VCC = 5.0V

35

pF

5. Not production tested in die form, characterized by chip design and tested in package.

4. -55˚C ≤ TJ ≤ +125˚C