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UPD75P0076 데이터시트(PDF) 14 Page - Renesas Technology Corp

부품명 UPD75P0076
상세설명  MOS INTEGRATED CIRCUIT
PDF  64 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD75P0076 데이터시트(HTML) 14 Page - Renesas Technology Corp

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µPD75P0076
12
Data Sheet U10232EJ1V1DS
3.4 Handling of Unused Pins
Pin
Recommended connection
P00/INT4
Connect to VSS or VDD
P01/SCK
Independently connect to VSS or VDD through
P02/SO/SB0
resistor
P03/SI/SB1
Connected to VSS
P10/INT0, P11/INT1
Connect to VSS or VDD
P12/TI1/INT2
P13/TI0
P20/PTO0
Input mode
: independently connected to VSS
P21/PTO1
or VDD through resistor
P22/PCL
Output mode : open
P23/BUZ
P30/MD0 to P33/MD3
P40/D0 to P43/D3
Connected to VSS
P50/D4 to P53/D7
P60/KR0/AN4 to P63/KR3/AN7
Input mode
: independently connected to VSS
or VDD through resistor
Output mode : open
P110/AN0 to P113/AN3
Connected to VSS or VDD
XT1Note
Connect to VSS or VDD
XT2Note
Open
VPP
Make sure to connect directly to VDD
AVREF
Connect to VSS
AVSS
Note
When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).



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