UPD75P0116CU datasheet(39/63 Pages) RENESAS

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µPD75P0116

Data Sheet U12603EJ1V1DS

AC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle

tCY

Operates with main system clock

2.0

128

µs

timeNote 1

(minimum instruction

execution time = 1

machine cycle)

Operates with subsystem clock

114

122

125

µs

TI0 input frequency

fTI

VDD = 2.7 to 5.5 V

1.0

MHz

275

kHz

TI0 high-, low-level

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

µs

widths

1.8

µs

Interrupt input high-, tINTH,

INT0

IM02 = 0

Note 2

µs

low-level widths

tINTL

IM02 = 1

µs

INT1, 2, 4

µs

KR0-KR7

µs

RESET low-level width

tRSL

µs

RC oscillation

fCC

R = 22 k

Ω,VDD = 2.7 to 5.5 V

0.9

1.0

1.3

MHz

frequency

C = 22 pF

VDD = 1.8 to 5.5 V

0.55

1.0

1.3

MHz

Notes 1. The cycle time of the CPU clock (

φ) (minimum instruction execution time) when the device operates with

the main system clock is determined by the time constant of the connected resistor (R) and capacitor

(C), and the value of the processor clock control register (PCC). When the device operates with the

subsystem clock, the cycle time of the CPU clock (

φ) is determined by the oscillation frequency of the

connected oscillator (and external clock), and the values of the system clock control register (SCC) and

processor clock control register (PCC).

The figure on the below shows the supply voltage VDD vs. cycle time tCY characteristics when the device

operates with the main system clock.

2. 2tCY or 128/fCC depending on the setting of the interrupt mode register (IM0).

0.5

Supply voltage VDD [V]

5.5

1.8

128

(with main system clock)

tCY vs VDD

Operation guaranteed range

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