© 2006 Microchip Technology Inc.

DS22003B-page 19

MCP3421

High Speed Mode

Clock frequency

0—

3.4

1.7

MHz

MHz

Clock high time

THIGH

60

120

——

ns

ns

Clock low time

TLOW

160

320

——

ns

SCL rise time (Note 1)

TR

——

40

80

ns

SCL fall time (Note 1)

TF

——

40

80

ns

SDA rise time (Note 1)

TR: DAT

——

80

160

ns

SDA fall time (Note 1)

TF: DATA

——

80

160

ns

START condition hold time

THD:STA

160

—

—

ns

After this period, the first clock

pulse is generated

Repeated START condition

setup time

160

—

—

ns

Only relevant for repeated Start

condition

Data hold time (Note 4)

THD:DAT

0

0

—70

150

ns

Data input setup time

TSU:DAT

10

—

—

ns

STOP condition setup time

TSU:STO

160

—

—

ns

STOP condition hold time

THD:STD

160

—

—

ns

Output valid from clock

(Notes 2 and 3)

TAA

—

—

150

310

ns

Bus free time

TBUF

160

—

—

ns

Time between START and STOP

conditions.

Input filter spike suppression

(Note 5)

TSP

0

—

10

ns

SDA and SCL pins

TABLE 5-4:

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note 1:

This parameter is ensured by characterization and not 100% tested.

2:

3:

If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this

4:

5:

This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.