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MP1909 데이터시트(PDF) 10 Page - Monolithic Power Systems

부품명 MP1909
상세설명  30V, 2.2MHz, 2A Half-Bridge Gate Driver in SOT583 Package
PDF  15 Pages
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제조업체  MPS [Monolithic Power Systems]
홈페이지  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP1909 데이터시트(HTML) 10 Page - Monolithic Power Systems

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MP1909
– 30V, HIGH-FREQUENCY HALF-BRIDGE GATE DRIVER
MP1909 Rev. 1.0
www.MonolithicPower.com
10
7/10/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
OPERATION
Theory of Operation
The MP1909 can drive two N-channel MOSFETs
in a synchronous buck or boost converter
topology. It can work at a 12V gate drive voltage
to minimize the external MOSFET
’s RDS(ON) and
achieve higher efficiency. A single PWM input
signal can generate the well-controlled high-side
and low-side drivers.
100% Duty Cycle
The high-side driver can turn on with 100% duty
cycle as long as the difference between VCC and
VIN exceeds 3.4V.
Switch Shoot-Through Protection
Internal anti-shoot-through circuitry protects the
high-side and low-side MOSFETs from turning
on at the same time. Adaptive dead time control
greatly reduces the dead time and switching
power loss.
When the PWM input goes high, the DRVL pin
goes low. The time it takes for the low-side
MOSFET (LS-FET) to turn off is determined by
the total gate charge. The MP1909 monitors the
LS-
FET’s VGS and level shifts this voltage
information to the high-side driver. The high-side
driver does not turn on the high-side MOSFET
(HS-FET) until the LS-FET is completely turned
off.
Under-Voltage Lockout
When BST-SW goes below its under-voltage
lockout (UVLO) threshold, the DRVH
pin’s output
goes low to turn off the HS-FET.
When VCC falls below its UVLO threshold, both
the DRVH and DRVL outputs go low to turn off
the MOSFETs.
Table 1 lists the operation of the HS-FET and
LS-FET
under
different
PWM
and
UVLO
conditions.
Table 1: States of Driver Outputs under Different Conditions
EN
BST-SW Voltage
VCC Voltage
PWM
DRVH
DRVL
Operating
Conditions
0
X
X
X
250kΩ
pull-down
resistor
250kΩ
pull-down
resistor
X
1
Above UVLO
Above UVLO
1
1
0
Normal operation
Above UVLO
Above UVLO
0
0
1
Falls below UVLO
Above UVLO
1
0
0
Falls below UVLO
Above UVLO
0
0
1
Above UVLO
Falls below UVLO
X
0
0
Normal-to-tripped
transition
Below UVLO
Falls below UVLO
X
0
0
Note:
9)
“X” means not applicable.



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