MP4541

– 80V, 0.8A, SYNCHRONOUS STEP-DOWN CONVERTER

MP4541 Rev. 1.0

MonolithicPower.com

15

5/28/2021

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© 2021 MPS. All Rights Reserved.

The output voltage ripple can be estimated with

Equation (10):

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V

(1

) (R

)

f

L

V

8 f

C





 











(10)

With

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency and causes the majority of the output

voltage ripple. For simplification, the output

voltage ripple can be estimated with Equation

(11):

OUT

OUT

OUT

2

SW

OUT

IN

VV

V

(1

)

8 f

C

L

V





 







(11)

With POSCAP capacitors, the ESR dominates

the impedance at the switching frequency. For

simplification, the output ripple can be estimated

with Equation (12):

OUT

OUT

OUT

ESR

SW

IN

VV

V

(1

) R

f

L

V





 





(12)

Selecting

a

larger-value

output

capacitor

provides

faster

load

transient

response.

However, the maximum output capacitor limit

should be considered when designing for

application. If the output capacitor value is too

high, the output voltage cannot reach the

required value during the SS time, and the

capacitor may fail to regulate. The maximum

output capacitor value (CO_MAX) can be estimated

with Equation (13):

O _ MAX

LIM _ AVG

OUT

SS

OUT

C

(I

I

)

t

/ V







(13)

Where ILIM_AVG is the average start-up current

during soft start, and tSS is the SS time.

Design Example

Table 1 shows a design example following the

application

guidelines

for

the

provided

specifications.

Table 1: Design Example

VIN

8V to 80V

VOUT

5V/0.8A

fSW

420kHz

Figure 4 on page 17 shows the detailed

application

schematics.

For

the

typical

performance and circuit waveforms, see the

Typical Performance Characteristics section.

For more device applications, refer to the related

evaluation board datasheet.