PHT4NQ10LT

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 28 October 2011

3 of 13

NXP Semiconductors

PHT4NQ10LT

N-channel TrenchMOS logic level FET

Fig 1.

Safe operating area; continuous and peak drain

currents as a function of drain-source voltage

Fig 2.

Normalized continuous drain current as a

function of solder point temperature

Unclamped inductive load; VDD ≤ 15 V;

RGS = 50 Ω; VGS = 5 V; starting Tj = 25 °C and 125 °C.

Fig 3.

Normalized total power dissipation as a

function of solder point temperature

Fig 4.

Non-repetitive avalnche ruggednes current as a

function of pulse duration

03ac48

10-2

10-1

1

10

102

110

102

103

VDS

I

D

(A)

D.C.

100 ms

10 ms

1 ms

tp= 10 µs

100 µs

tp

tp

T

P

t

T

δ =

RDSon = VDS/ ID

Tsp (°C)

0

200

150

50

100

03aa25

40

80

120

Ider

(%)

0

Tsp (°C)

0

200

150

50

100

03aa17

40

80

120

Pder

(%)

0

03ac92

10−1

1

10

10−2

10−1

110

t p (ms)

IAS

(A)

Tj prior to avalanche = 125

°C

25

°C