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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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APEX20K 데이터시트(PDF) 39 Page - Altera Corporation |
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APEX20K 데이터시트(HTML) 39 Page - Altera Corporation |
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39 / 117 page  Altera Corporation 39 APEX 20K Programmable Logic Device Family Data Sheet Figure 25. APEX 20K Bidirectional I/O Registers Note (1) Note to Figure 25: (1) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. VCC OE[7..0] CLK[1..0] ENA[5..0] CLRn[1..0] Peripheral Control Bus CLRN D Q ENA VCC 2 Dedicated Clock Inputs Chip-Wide Output Enable CLK[3..2] 2 12 VCC VCC Chip-Wide Reset Input Pin to Core Delay Slew-Rate Control VCCIO Optional PCI Clamp Output Register t Delay Core to Output Register Delay Input Pin to Input Register Delay CLRN DQ ENA VCC Chip-Wide Reset Input Register Output Register CLRN DQ ENA Chip-Wide Reset VCC OE Register VCC 4 Dedicated Inputs Row, Column, or Local Interconnect CO Open-Drain Output |
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