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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7L15 데이터시트(PDF) 61 Page - STMicroelectronics |
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ST7L15 데이터시트(HTML) 61 Page - STMicroelectronics |
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61 / 138 page  ST7L15, ST7L19 61/138 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) – At the second input capture on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: LTICR = LT2 ATICRH = ATH2 ATICRL = ATL2 Hence ATICR2 [11:0] = ATH2 & ATL2 Now pulse width P between first capture and sec- ond capture will be: P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec- imal ((FFF * N) + N + ATICR2 - ATICR1 – 1) * 1ms where N = No of overflows of 12-bit CNTR1. Figure 43. Long Range Input Capture Timing Diagram F9h 00h LT1 F9h 00h LT2 ATH1 & ATL1 00h 0h LT1 ATH1 LT2 ATH2 fOSC/32 TB Counter1 CNTR1 LTIC LTICR ATICRH 00h ATL1 ATL2 ATICRL ATICR = ATICRH[3:0] & ATICRL[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ATH2 & ATL2 _ _ _ 1 |
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