Data Sheet S15381EJ1V0DS

12

µµµµPD161602A/B

4.3 CLK Signal Input

Input at least 4 clocks of the CLK signal after the rising of the STB signal.

STB

CLK

STH

Internal latch

signal1

Internal latch

signal2

Internal latch

signal3

/1

2

3

4

5

6

1

2

3

4

7

8

Note

Invalid D0 to D3 D4 to D6 D7 to D9 D10 to D12

D13 to D15

D16 to D18

D19 to D21

Note

Note

Note Internal latch signal : It is the signal that do latch the display data put in data register in output latch circuit.

5. MODE EXPLANATION

Normal Mode/ 8-clor Display Mode

CM

POL

Data

Driver Output Status

Driver Output (in normally white)

MSB = H

White level display

H

MSB = L

Black level display

MSB = H

White level display

H

L

MSB = L

8-color mode

Black level display

All bit = H

White level display

H

All bit = L

Black level display

All bit = H

White level display

L

L

All bit = L

260,000-color mode

Black level display