TS922AIN datasheet(14/21 Pages) STMICROELECTRONICS

14 / 21 page

Package mechanical data

TS922

14/21

Package mechanical data

In order to meet environmental requirements, STMicroelectronics offers these devices in

ECOPACK® packages. These packages have a Lead-free second level interconnect. The

category of second level interconnect is marked on the package and on the inner box label,

in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics

trademark. ECOPACK specifications are available at: www.st.com.

5.1

Flip-chip package (8 bumps)

Figure 14.

Top view and dimensions of 8-bump flip-chip

Figure 15.

Flip-chip footprint recommendation

■ Die size: 1600µm x 1600µm ±30µm

■ Die height: 350µm ±20µm

■ Die height (including bumps):

600µm

■ Bumps diameter: 315µm ±50µm

■ Bumps height: 250µm ±40µm

■ Pitch: 500µm ±10µm

600 µm

1600 µm

500µm

∅ 315µm

600 µm

1600 µm

500µm

∅ 315µm

Pad in Cu 18

μm with Flash NiAu (6μm, 0.15μm)

150

μm min.

500

μm

500

μm

Φ=250μm

Φ=400μm

75µm min.

100

μm max.

Track

Solder mask opening

TS922IJ Footprint

Pad in Cu 18

μm with Flash NiAu (6μm, 0.15μm)

150

μm min.

500

μm

500

μm

Φ=250μm

Φ=400μm

75µm min.

100

μm max.

Track

Solder mask opening

Pad in Cu 18

μm with Flash NiAu (6μm, 0.15μm)

150

μm min.

500

μm

500

μm

Φ=250μm

Φ=400μm

75µm min.

100

μm max.

Track

Solder mask opening

TS922IJ Footprint

TS922AIN 데이터시트(PDF) 14 Page - STMicroelectronics

TS922AIN 데이터시트(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

데이터시트 다운로드

링크 URL