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STE100A 데이터시트(PDF) 60 Page - STMicroelectronics

부품명 STE100A
상세설명  PCI 10/100 Ethernet controller with integrated PHY (3.3V)
PDF  82 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE100A 데이터시트(HTML) 60 Page - STMicroelectronics

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Registers and descriptors description
STE10/100A
60/82
12
10FD
10BASE-T full duplex ability.
Always 1, since STE10/100A has 10Base-T full
duplex ability.
1RO
11
10HD
10BASE-T half duplex ability.
Always 1, since STE10/100A has 10Base-T half
duplex ability.
1RO
10~6
---
Reserved
0RO
5ANC
Auto-negotiation completed.
0: Auto-negotiation process incomplete.
1: Auto-negotiation process complete.
0RO
4RF
Result of remote fault detection.
0: no remote fault condition detected.
1: remote fault condition detected.
0RO/LH*
3AN
Auto-negotiation ability.
Always 1, since STE10/100A has auto-
negotiation ability.
1RO
2LINK
Link status.
0: a link failure condition occurred. Readin clears
this bit.
1: valid link established.
0RO/LL*
1JAB
Jabber detection.
1: jabber condition detected (10Base-T only).
0RO/LH*
0
EXT
Extended register support.
Always 1, since STE10/100A supports extended
register
1RO
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
XR2(offset = bch) - PID1, PHY identifier 1
15~0
PHYID1
Part one of PHY identifier.
Assigned to the 3rd to 18th bits of the
Organizationally Unique Identifier (The ST OUI
is 0080E1 hex).
1C04h
RO
XR3(offset = c0h) - PID2, PHY identifier 2
15~10
PHYID2
Part two of PHY identifier.
Assigned to the 19th to 24th bits of the
organizationally unique identifier (OUI).
000000b
RO
9~4
MODEL
Model number of STE10/100A.
6-bit manufacturer’s model number.
000001b
RO
3~0
REV
Revision number of STE10/100A.
4-bits manufacturer’s revision number.
0000b
RO
Table 10.
Transceiver registers description (continued)
Bit #
Name
Description
Default
RW type



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