전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

MAS9560 데이터시트(PDF) 22 Page - Micro Analog systems

부품명 MAS9560
상세설명  Stereo Audio Driver DAC
PDF  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MAS [Micro Analog systems]
홈페이지  http://www.mas-oy.com
Logo MAS - Micro Analog systems

MAS9560 데이터시트(HTML) 22 Page - Micro Analog systems

Back Button MAS9560 Datasheet HTML 17Page - Micro Analog systems MAS9560 Datasheet HTML 18Page - Micro Analog systems MAS9560 Datasheet HTML 19Page - Micro Analog systems MAS9560 Datasheet HTML 20Page - Micro Analog systems MAS9560 Datasheet HTML 21Page - Micro Analog systems MAS9560 Datasheet HTML 22Page - Micro Analog systems MAS9560 Datasheet HTML 23Page - Micro Analog systems MAS9560 Datasheet HTML 24Page - Micro Analog systems MAS9560 Datasheet HTML 25Page - Micro Analog systems  
Zoom Inzoom in Zoom Outzoom out
 22 / 25 page
background image
22 (25)
DA9560.001
20 January, 2005
Right AUX Gain Register 0x09
R/W
0
-
0x09[7:5]
-
-
Unused
ARV[4:0] Right AUX pre-amplifier gain
ARV
0x09[4:0]
R/W
00000
00000
00001
...
10101...11111
Mute
-20 dB
in steps of 2 dB
20 dB
AIN Gain Register
0x0A
R/W
0
-
0x0A[7:5]
-
-
Unused
AIV[4:0] AIN pre-amplifier gain
AIV
0x0A[4:0]
R/W
00000
00000
00001
...
10101...11111
Mute
-20 dB
in steps of 2 dB
20 dB
Note: Unused register bit values are undefined.
I2C BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40
°C ≤ TA ≤ +85°C, typical
values at TA = +27°C, unless otherwise noted
Parameter
Pin Name Conditions
Min
Nom
Max
Unit
Input Low Voltage
SCLK,
SDI
tbd
IOVDD
Input High Voltage
SCLK,
SDI
tbd
IOVDD
Start Condition Setup
Time
SCLK,
SDI
tbd
ns
Stop Condition Setup
Time
SCLK,
SDI
tbd
ns
Data Setup Time before
clock rising edge
SCLK,
SDI
tbd
ns
Data Hold Time after
clock falling edge
SCLK,
SDI
tbd
ns
Clock Low Pulse Time
SCLK
tbd
ns
Clock High Pulse Time
SCLK
tbd
ns
Bus Frequency
SCLK
tbd
MHz
Data Output Low Voltage
SCLK,
SDI
ILOAD = 3
mA
tbd
V
Data Output High
Leakage Current
SCLK,
SDI
VSDI = 5 V
tbd
µA
Data Output Hold Time
after clock falling edge
SCLK,
SDI
tbd
ns
Data Output Setup Time
before clock rising edge
SCLK,
SDI
fI2C = 1MHz
tbd
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com