STA323W_06 datasheet(39/71 Pages) STMICROELECTRONICS

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STA323W

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Figure 49.

Serial input and data timing

7.3.1

Delay serial clock enable

Each channel received from the I2S can be mapped to any internal processing channel via

the channel input mapping registers. This allows processing flexibility. The default settings of

these registers map each I2S input channel to its corresponding processing channel.

1010

Right-justified 18-bit data

1110

Right-justified 16-bit data

Table 23.

Serial input data timing characteristics (Fs = 32 to 192 kHz)

Signal

Frequency

BICKI frequency (slave mode)

12.5 MHz max.

BICKI pulse width high (T1) (slave mode)

40 ns min.

BICKI active to LRCKI edge delay (T2)

20 ns min.

BICKI active to LRCKI edge delay (T3)

20 ns min.

SDI valid to BICKI active setup (T4)

20 ns min.

BICKI active to SDI hold time (T5)

20 ns min.

Table 22.

Supported serial audio input formats (continued)

BICKI

SAI (3...0)

SAIFB

Interface format

Table 24.

Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 25.

Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

C1IM

0: processing channel 1 receives left I2S input

1: processing channel 1 receives right I2S input

7R/W

C2IM

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

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