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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TS4956 데이터시트(PDF) 47 Page - STMicroelectronics |
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TS4956 데이터시트(HTML) 47 Page - STMicroelectronics |
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47 / 51 page  TS4956 Package mechanical data 47/51 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.1 18-bump flip-chip package Figure 134. Footprint recommendations Die size: 2.5x2.4 mm ± 30µm Die height (including bumps): 600µm Bumps diameter: 315µm ±50µm Bump diameter before reflow: 300µm ±10µm Bumps height: 250µm ±40µm Die height: 350µm ±20µm Pitch: 500µm ±50µm Coplanarity: 50µm max 866 µm 866 µm 500 µm 750 µm 2500 µm 2400 µm 600 µm 866 µm 866 µm 500 µm 750 µm 2500 µm 2400 µm 600 µm |
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