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RT6318B 데이터시트(PDF) 22 Page - Richtek Technology Corporation

부품명 RT6318B
상세설명  8A, 23V Synchronous Step-Down Converter with 3.3V/5V LDO
PDF  25 Pages
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제조업체  RICHTEK [Richtek Technology Corporation]
홈페이지  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT6318B 데이터시트(HTML) 22 Page - Richtek Technology Corporation

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RT6318B/C
22
DS6318B/C-01 December 2021
www.richtek.com
©
Copyright 2021 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
GND
LX
LX
BOOT
VIN
EN
PGND
6
1
2
4
5
3
7
Rboot
COUT
VOUT
L
GND
CIN
VIN
The input capacitor must
be placed as close to the
IC as possible for noise
immunity and phase ring.
The compensation components(RFF and
CFF) must be connected as close to the IC
as possible.
LX should be connected to
inductor by wide and short trace,
and Do NOT use any via for LX.
Keep sensitive components
away from this area.
The VIN trace should be wide
enough for high current density
application.
The number of vias is base on
input maximum current to design.
The AGND and PGND should be
connected by single point grounding to
avoid ground level shift.
RFF
11 10 9
8
12
For thermal performance, the vias
under IC must be placed and least
two layers for VIN and PGND trace.
The recommended via size is 8 mil
drill/16 mil copper width.
CFF
GND
RT6318B
GND
LX
LX
BOOT
VIN
EN
PGND
6
1
2
4
5
3
7
GND
Rboot
COUT
VOUT
L
GND
CIN
VIN
The input capacitor must
be placed as close to the
IC as possible for noise
immunity and phase ring.
LX should be connected to
inductor by wide and short trace,
and Do NOT use any via for LX.
Keep sensitive components
away from this area.
The VIN trace should be wide
enough for high current density
application.
The number of vias is base on
input maximum current to design.
The AGND and PGND should be
connected by single point grounding to
avoid ground level shift.
11 10 9
8
12
For thermal performance, the vias
under IC must be placed and least
two layers for VIN and PGND trace.
The recommended via size is 8 mil
drill/16 mil copper width.
AGND
RT6318C
The compensation components(RFF and
CFF) must be connected as close to the IC
as possible.
Figure 9. Layout Guide of RT6318C
Figure 8. Layout Guide of RT6318B



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