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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TAS5504 데이터시트(PDF) 58 Page - Texas Instruments |
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TAS5504 데이터시트(HTML) 58 Page - Texas Instruments |
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58 / 96 page  Serial Audio Interface Control and Timing 51 SLES123 − October 2004 TAS5504 3.7.2 Left Justified Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5504 masks unused trailing data bit positions. 23 22 SCLK 32 Clks LRCLK Left Channel 24-Bit Mode 9 8 5 4 1 0 MSB LSB 23 22 32 Clks LRCLK Right Channel 9 8 5 4 1 0 MSB LSB NOTE: All data presented in 2s complement form with MSB first. 18 20-Bit Mode 5 4 1 0 19 14 16-Bit Mode 1 0 15 18 5 4 1 0 19 14 1 0 15 2-Channel Left-Justified Stereo Input Figure 3−10. Left Justified 64 Fs Format |
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