M95320-R datasheet(11/44 Pages) STMICROELECTRONICS

11 / 44 page

M95320, M95640, M95320-x, M95640-x

Operating features

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Operating features

4.1

Supply voltage (VCC)

4.1.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a

suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package

pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

4.1.2

Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip

Select (S) is not allowed to float but must follow the VCC voltage, therefore the S line should

be connected to VCC via a suitable pull-up resistor.

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after Power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been High, prior to going Low to start the first operation.

The VCC rise time must not be faster than 1V/µs.

4.1.3

Internal device Reset

In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)

circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any

instruction until VCC has reached the Power On Reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Tables XX).

When VCC has passed the POR threshold, the device is reset and in the following state:

●

Standby Power mode

●

deselected (at next Power-up, a falling edge is required on Chip Select (S) before any

instructions can be started).

●

not in the Hold Condition

Status Register state:

●

the Write Enable Latch (WEL) is reset to 0

●

Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status

volatile bits).

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