Nexperia

PUSB3FA2

ESD protection for ultra high-speed interfaces

VCL (V)

0

8

6

2

4

aaa-023076

4

2

6

8

IPP

(A)

0

IEC 61000-4-5; tp = 8/20 µs; positive pulse

Fig. 13. Dynamic resistance with positive clamping;

typical values

VCL (V)

-8

0

-2

-6

-4

aaa-023077

-4

-6

-2

0

IPP

(A)

-8

IEC 61000-4-5; tp = 8/20 µs; negative pulse

Fig. 14. Dynamic resistance with negative clamping;

typical values

9. Application information

The device is designed to provide high-level ESD protection for high-speed serial data buses such

as HDMI, DisplayPort, eSATA and LVDS data lines.

Note: When designing the PCB, give careful consideration to impedance matching and

signal coupling. Do not connect the signal lines to unlimited current sources like, for

example, a battery.

Dynamic resistance

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the ESD

protection during an ESD event. Do not connect unlimited DC current sources to the data lines to

avoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage

(due to an ESD pulse for instance).

PUSB3FA2

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2018. All rights reserved

Product data sheet

5 April 2018

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