Custom Silicon Solutions, Inc. ©2009

2

Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Block Diagrams

Standard 555 Timer Configuration (Std. Mode)

(Programmable counter bypassed, Divider setting = 1)

Figure 3

Extended Period Configuration (EP Mode)

(Programmable counter enabled, Divider setting ≥ 10)

Figure 4

EEPROM Bit Assignments

Counter

Configuration

Divider Setting

(Mult)

Mode

Control Bits

Function

xxxxx000

1 (Std. 555)

xxxx0xxx

Astable Mode (“Don’t Care” if Std. 555)

xxxxx001

10

xxxx1xxx

Monostable Mode (“Don’t Care” if Std. 555)

xxxxx010

100

xxx0xxxx

Micro Power

xxxxx011

1K

xxx1xxxx

Low Power

xxxxx100

10K

xx0xxxxx

Standard Voltage (Trip levels = ⅓ & ⅔ VDD)

xxxxx101

100K

xx1xxxxx

Low Voltage (Trip levels = 10% & 90% VDD)

xxxxx110

1M

Bit 6

Unused

xxxxx111

1 (Std. 555)

Bit 7

1 (Read Only)

Table 1A

Table 1B

Note: For detailed programming information, see Application Note AN555-1 (CSS555_App_Note1_Serial_Interface)

_

+

Comp

_

+

Comp

R

S

Q

Q

Reset

Flip

Flop

VDD

Trigger

Output

Control Voltage

Threshold

VH

VL

R1

R2

R3

Reset

VSS

1

5

6

4

8

2

Discharge

3

7

R1+R2+R3 ~ 6 MΩ

For VDD > 1.8V, VH = 2/3 x VDD, VL = 1/3 x VDD

For VDD < 1.8V, VH = 0.9 x VDD, VL = 0.1 x VDD

CTI

100pF

VDD

_

+

Comp

_

+

Comp

R

S

Q

Q

Reset

Flip

Flop

Control Voltage

Threshold

VH

VL

R1

R2

R3

Reset

VSS

1

5

6

4

8

Trigger

2

Enbl

Clk

Q

Reset

6 Decade

Counter

Sel

Clk

Run

Q

Reset

Trig

Mode

Control

Mode

Output

Discharge

3

7

In0

In1

Out

Sel

2:1 Mux

Configuration

EEPROM

CTI

100pF