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April 2001

s

HIGH SPEED:

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 163

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74AC163 is an advanced high-speed CMOS

SYNCRONOUS

PRESETTABLE

COUNTER

fabricated

with

sub-micron silicon gate and

4 bit binary counter with Synchronous Clear.

The circuit have four fundamental modes of

operation, in order of preference: synchronous

reset, parallel load, count-up and hold. Four

control inputs, Master Reset (CLEAR), Parallel

Enable Input (LOAD), Count Enable Input (PE)

and Count Enable Carry Input (TE), determine the

mode of operation as shown in the Truth Table. A

LOW signal on CLEAR overrides counting and

parallel loading and sets all outputs on LOW state

on the next rising edge of CLOCK. A LOW signal

on

LOAD

overrides

counting

and

allows

information on Parallel Data inputs to be loaded

into the flip-flop on the next rising edge of CLOCK.

With LOAD and CLEAR HIGH, PE and TE permit

counting when both are HIGH. Conversely, a

LOW signal on either PE and TE inhibits counting.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74AC163

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

74AC163B

SOP

74AC163M

74AC163MTR

TSSOP

74AC163TTR

TSSOP

DIP

SOP