2.3

ES9018S Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

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De-emphasis

The de-emphasis feature is included for audio data that has utilized the 50/15

s pre-emphasis for noise reduction. There are three de-emphasis

filters, one for 32kHz, one for 44.1kHz, and one for 48kHz.

The de-emphasis filter can automatically be applied when an SPDIF stream sets the de-emphasis flag. It will auto detect the sample rate (32k,

44.1k, 48k) in either consumer or professional formats and then apply the correct de-emphasis filter. The automatic enabling of the de-emphasis

filter can be disabled in Register 17 <en_auto>.

OSF Bypass

The oversampling FIR filter can be bypassed, sourcing data directly into the IIR filter. ESS recommends using 8 x Fs as the input. For example, an

external signal at 44.1kHz can be oversampled externally to 8 x 44.1kHz = 352.8kHz and then applied to the serial decoder in either I2S, LJ or RJ

format. The maximum sample rate that can be applied is 1.536MHz (8 x 192kHz).

SPDIF Data Select

An SPDIF source multiplexer allows for up to eight SPDIF sources to be connected to the data pins on the SABRE32 Reference. The SABRE32

Reference uses an internal programmable register to select the appropriate data pin to decode.

SPDIF input can be automatically decoded when there is valid SPDIF data if Register 17 <spdif_autodetect> is enabled.

Programmable Filter

The FIR filter can be programmed with custom coefficients to achieve an arbitrary frequency response that suits the needs of the product. The two

stage interpolated filter exploits the symmetry of the coefficients to achieve a very sharp frequency response while using only 64 coefficients for the

stage one filter and 14 coefficients for the stage two filter. Custom coefficients can be enabled via register 37 <prog_coeff_enabled> and can be

programmed via the method explained in the FIR Programmable Filters section.

The length of the stage 2 filter is configurable to either 27 or 28 coefficients via register 17 <fir_length>.

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry. Maximum MCLK frequency is 100MHz. The system

clock must also satisfy:

Data Type

Valid MCLK Frequencies

DSD Data

100MHz > MCLK > 3 x Fs, Fs = 2.8224MHz (x 1, 2, or 4)

Serial Normal Mode

100MHz > MCLK > 192 x Fs, Fs

 200kHz, or

100MHz > MCLK > 256 x Fs, 200kHz < Fs

 384kHz

Serial OSF Bypass Mode

100MHz > MCLK > 24 x Fs, Fs

 1.536MHz

SPDIF Data

100MHz > MCLK > 386 x Fs, Fs

 200kHz

Table 7 - MCLK configurations