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ES9068A 데이터시트(PDF) 2 Page - ESS Technology,Inc |
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ES9068A 데이터시트(HTML) 2 Page - ESS Technology,Inc |
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2 / 3 page ![]() ES9068A March 31, 2021 0.2 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • www.esstech.com 2 Functional Block Diagram PLL I2C MASTER Low Noise Reg CLOCK NETWORK DIGITAL CORE XI XO SDAM SCLM RESETB DCLK (BCK) DATA1 (WS) DATA2 (SD) GPIO1-11,14 AGND_DAC DVDD AVDD AVCC_DAC VREF VCCA GND (Exposed Pad) DACB_L DAC_L DACB_R DAC_R AVCC_33 AVCC_18 HyperStream © II QUAD DAC HyperStream © II QUAD DAC MIC LDO BANDGAP CLK DETECT / POR DIGITAL AUDIO PORT (I2S, DSD, DoP, SPDIF, MQA) RT1 INT SMART CONTROLLER Bootload Interface/SPI MBIAS I2C SLAVE SDAS SCLS ACLK1 ADDR DVDD LDO DIFF. MIC ADC AMIC_P AMIC_N PRE-AMP Differential 0dB-30dB, 6 dB Steps PRE-AMP S/E ADC (RIGHT) ADC_R PRE-AMP S/E ADC (LEFT) ADC_L CHARGE PUMP 1.8V PNEG C1 C2 Figure 1 - ES9068ABlock Diagram |
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