ES9281A/80A PRO Product Brief

0.2.5

April 15, 2021

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-

8800 • WWW.ESSTECH.COM

Functional Block Diagram

PLL

I2C MASTER

Low Noise Reg

CLOCK

NETWORK

POWER

MANAGEMENT

& CONTROL

HP AMP

+

-

100

100

R

HP AMP

+

-

100

100

R

DIGITAL CORE

XI

XO

SDAM

SCLM

RESETB

DCLK (BCK)

DATA1 (WS)

DATA2 (SD)

GPIO1*-14

DGND DVDD

AVDD

AVCC_DAC

VREF

VCCA

AGND

PNEG

PNEG_VC

OUT_L

INB_L

GSN_L

IN_L

INB_R

OUT_R

IN_R

ADC_R

GSN_R

AVCC_33

AVCC_18

HyperStream® II

QUAD DAC

HyperStream® II

QUAD DAC

CHARGE

PUMP

CLASS G

1.8/3.3V

C1

C2

C1_VC

C2_VC

Jack/Button Detection

•

Plug In & Out

•

Impedance Detection

•

Buttons

•

Moisture protection

ADC_L

JDET1

JDET2

MIC

LDO

S/E ADC

(LEFT)

DIFF. MIC ADC

AMIC_P

AMIC_N

PRE-AMP

Differen tial

BANDGAP

CLK DETECT / POR

DIGITAL

AUDIO

PORT

(I2S,

DSD,

DoP,

SPDIF,

MQA)

RT1

INT

SMART CONTROLLER

Bootload Interface/SPI

0dB-30dB, 6 dB Steps

0dB-30dB,

6dB Steps

1Vrms Input

ASP

PB

ZREF

AGND

AGND

MBIAS

I2C SLAVE

SDAS

SCLS

ACLK2

ACLK1

ADDR

R

R

PRE-AMP

PRE-AMP

S/E ADC

(RIGHT)

DVDD

LDO

VDDA

VUSB

USB PHY

D+

D-

VBUS

Figure 2 – ES9281A/80A PRO Block Diagram

*Note: SCLK/GPIO1 is usable as a GPIO when USB port is not used.