ADFS7124-8BBCPZ datasheet(64/93 Pages) AD

부품명	ADFS7124-8BBCPZ

상세설명	8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

PDF	93 Pages

Scroll/Zoom	100%

제조업체	AD [Analog Devices]

홈페이지	http://www.analog.com

Logo

64 / 93 page

Data Sheet

ADFS7124-8

DIGITAL FILTER

analog.com

Rev. 0 | 64 of 93

SINC3/SINC4

FILTER

MODULATOR

AVERAGING

BLOCK

POST

FILTER

Figure 109. Post Filters

Table 61 shows the output data rates with the accompanying

settling times and rejection.

When continuously converting on a single channel, the first conver-

sion requires a time of tSETTLE. Subsequent conversions occur at

1/fADC. When multiple channels are enabled (either manually or

using the sequencer), the settling time is required to generate a

valid conversion on each enabled channel.

Table 61. ADFS7124-8 Post Filters: Output Data Rate, Settling Time (tSETTLE), and Rejection

Output Data Rate

(SPS)

f3dB (Hz)

tSETTLE, Full Power

Mode (ms)

tSETTLE, Mid Power

Mode (ms)

tSETTLE, Low Power

Mode (ms)

Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ±

1 Hz (dB)1

27.27

17.28

38.498

38.998

39.662

15.12

41.831

42.331

42.995

13.38

51.831

52.331

52.995

16.67

12.66

61.831

62.331

62.995

1 Stable controllerclock used.

ADFS7124-8BBCPZ 데이터시트(PDF) 64 Page - Analog Devices

ADFS7124-8BBCPZ 데이터시트(HTML) 64 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

데이터시트 다운로드

링크 URL