www.ti.com

CLOCK AND DATA RECOVERY

MINIMUM TRANSITION DENSITY

JITTER TOLERANCE

SLK2511B

SLLS763B – JANUARY 2007 – REVISED MARCH 2007

Table 6. Reference Clock Frequency

REFCLKSEL

REFERENCE CLOCK FREQUENCY

0

622.08 MHz

1

155.52 MHz

The CDR unit of SLK2511B recovers the clock and data from the incoming data streams.

In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency

stability. If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the

LOL pin is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm.

The loop filter transfer function is optimized to enable the CDR to track ppm difference in the clocking and

tolerate the minimum transition density that can be received in a SONET data signal (

±20 ppm). The transfer

function yields a typical capture time of 3500 bit times for random incoming NRZ data after the device is

powered up and achieves frequency locking.

The device tolerates up to 72 consecutive digits (CID) without sustaining an error.

Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that

causes the equivalent 1-dB optical/electrical power penalty. This refers to the ability of the device to withstand

input jitter without causing a recovered data error. The device has a jitter tolerance that exceeds the mask

OC-N/STS-N

f0

F1

F2

F3

F4

A1

A2

A3

LEVEL

(Hz)

(Hz)

(Hz)

(kHz)

(kHz)

(Ulpp)

(Ulpp)

(Ulpp)

3

10

30

300

6.5

65

0.15

1.5

15

12

10

30

300

25

250

0.15

1.5

15

24

Not Specified

48

10

600

6000

100

1000

0.15

1.5

15

(1)

The tolerance margin is 20% or more at all modulating frequencies when measured using the HP 7150A jitter analysis system on the

Texas Instruments provided EVM.

Figure 2. Input Jitter Tolerance

8

Submit Documentation Feedback