CC2550-RTY1 datasheet(14/55 Pages) TI

14 / 55 page

CC2550

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 14 of 54

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

Hi-Z

Figure 6: Configuration registers write and read operations

Parameter

Description

Min

Max

Units

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between

address and data, and between each data byte (burst access).

MHz

SCLK

frequency, single access

No delay between address and data byte

MHz

fSCLK

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

6.5

MHz

tsp,pd

CSn

low to positive edge on SCLK, in power-down mode

200

µs

tsp

CSn

low to positive edge on SCLK, in active mode

tch

Clock high

tcl

Clock low

trise

Clock rise time

tfall

Clock fall time

Single access

tsd

Setup data (negative SCLK edge) to

positive edge on SCLK

(tsd applies between address and data bytes, and

between data bytes)

Burst access

thd

Hold data after positive edge on SCLK

tns

Negative edge on SCLK to CSn high

Table 14: SPI interface timing requirements

Figure 7: Register access types

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