CAT24C01/02/04/08/16

3

Doc No. 1115, Rev. C

© 2006 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Symbol

Parameter

Standard

Fast

Units

Min

Max

Min

Max

Clock Frequency

100

400

kHz

START Condition Hold Time

4

0.6

μs

Low Period of SCL Clock

4.7

1.3

μs

High Period of SCL Clock

4

0.6

μs

START Condition Setup Time

4.7

0.6

μs

Data In Hold Time

0

0

μs

Data In Setup Time

250

100

ns

SDA and SCL Rise Time

1000

300

ns

SDA and SCL Fall Time

300

300

ns

STOP Condition Setup Time

4

0.6

μs

Bus Free Time Between STOP and START

4.7

1.3

μs

SCL Low to Data Out Valid

3.5

0.9

μs

Data Out Hold Time

100

100

ns

Noise Pulse Filtered at SCL and SDA Inputs

100

100

ns

WP Setup Time

0

0

μs

WP Hold Time

2.5

2.5

μs

Write Cycle Time

5

5

ms

Power-up to Ready Mode

1

1

ms

Note:

(1) Test conditions according to “A.C. Test Conditions” table.

(2) Tested initially and after a design or process change that affects this parameter.

A.C. TEST CONDITIONS

Input Levels

Input Rise and Fall Times

Input Reference Levels

Output Reference Levels

Output Load