Discontinued

Parts

8

CAT25C01, CAT25C02, CAT25C04

Doc. No. 1105, Rev. B

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Figure 7. WRSR Timing

Figure 6. Write Instruction Timing

Note: Dashed Line= mode (1, 1) – ––––

*X=0 for 25010, 25020 ; X=A8 for 25040

Note: Dashed Line= mode (1, 1) – ––––

SK

SI

SO

00

00

00

10

BYTE ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

012345678

13

14

15

16

17

18

19

20

21

22

23

CS

OPCODE

DATA IN

HIGH IMPEDANCE

X*

A7

A0

0

1

2

345

67

8

10

911

12

13

14

SCK

SI

MSB

HIGH IMPEDANCE

DATA IN

15

SO

CS

7

6

5

4

3

2

10

00

0

00

0

0

1

OPCODE

During an internal write cycle, all commands will be

ignored except the RDSR (Read Status Register)

instruction.

The Status Register can be read to determine if the write

cycle is still in progress. If Bit 0 of the Status Register is

set at 1, write cycle is in progress. If Bit 0 is set at 0, the

device is ready for the next instruction.

Page Write

The CAT25C01/02/04 features page write capability.

After the initial byte, the host may continue to write up to

16 bytes of data to the CAT25C01/02/04. After each

byte of data received, lower order address bits are

internally incremented by one; the high order bits of

address will remain constant. The only restriction is that

the X (X=16 for CAT25C01/02/04) bytes must reside on

the same page. If the address counter reaches the end

of the page and clock continues, the counter will “roll

over” to the first address of the page and overwrite any

data that may have been written. The CAT25C01/02/04

is automatically returned to the write disable state at the

completion of the write cycle. Figure 8 illustrates the

page write sequence.

To write to the status register, the WRSR instruction

should be sent. Only Bit 2, Bit 3 and Bit 7 of the status

register can be written using the WRSR instruction.

Figure 7 illustrates the sequence of writing to status

register.