6

CAT1232LP/CAT1832

Doc. No. 25089, Rev. 0C

© 2006 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

WATCHDOG TIMER AND

ST

ST

ST

ST

ST INPUT

A watchdog timer stops and restarts a microprocessor

that has stopped proper operation or become “hung”.

The watchdog performs this function by monitoring the

ST input. After the reset outputs go inactive the ST input

must be strobed with a high-to-low signal transition prior

to the minimum watchdog timeout period. However if the

ST input is not strobed with a high-to-low signal transi-

tion prior to a watchdog timeout the reset outputs will

microprocessor. Once the resets return to the inactive

state the watchdog timer restarts the process.

The TD input allows the user to select from three

predetermined watchdog timeout periods. Always use

the minimum timeout period to determine the required

frequency of

ST high-to-low transitions and the maxi-

mum to determine the time prior to the reset outputs

becoming active.

ST pulse widths must be 20ns or

greater.

The watchdog timer cannot be disabled. It must be

strobed with a high-to-low signal transition to avoid a

watchdog timeout and subsequent reset.

Figure 6. Timing Diagram: Pushbutton Reset

RESET

RESET

PBRST

RESET

RESET

ST

Valid

Strobe

Valid

Strobe

Invalid

Strobe

Note:ST is ignored whenever a reset is active.

(Min)

(Min)

Figure 4. CAT1832 Application Circuit:

Pushbutton Reset

Figure 7. Timing Diagram: Strobe Input

Figure 5. CAT1232LP Application Circuit: Watchdog Timer

PBRST

3.3V

1

VCC

TD

2

ST

TOL

CAT1832

µP

3

4

RESET

GND

8

7

6

5

RESET

RESET

I/O

PBRST

5V

1

10k

VCC

TD

2

ST

TOL

CAT1232LP

µP

Decoder

3

4

RESET

GND

8

7

6

5

RESET

MREQ

Address

Bus

RESET

e

g

a

t

l

o

V

D

T

l

e

v

e

L

)

s

m

(

d

o

i

r

e

P

t

u

o

-

e

m

i

T

g

o

d

h

c

t

a

W

N

I

ML

A

N

I

M

O

NX

A

M

D

N

G5

.

2

60

5

10

5

2

g

n

i

t

a

o

l

F0

5

20

0

60

0

0

1

C

0

0

50

0

2

10

0

0

2