WM8590GEDSSLASHRV datasheet(31/51 Pages) WOLFSON

31 / 51 page

Production Data

WM8590

PD Rev 4.0 January 2006

Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to

write the same attenuation value to both left and right volume control registers, saving on software

writes.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

LAG[7:0]

11001111

(0dB)

Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See

Table 10.

R14 (0Eh)

0001110

Attenuation

ADCL

ZCLA

Left Channel ADC Zero Cross Enable:

0: Zero cross disabled

1: Zero cross enabled

7:0

RAG[7:0]

11001111

(0dB)

Attenuation data for right channel ADC gain in 0.5dB steps. See

Table 10.

R15 (0Fh)

0001111

Attenuation

ADCR

ZCRA

Right Channel ADC Zero Cross Enable:

0: Zero cross disabled

1: Zero cross enabled

MUTERA

Mute for Right Channel ADC

0: Mute Off

1: Mute on

MUTELA

Mute for Left Channel ADC

0: Mute Off

1: Mute on

ZCSCRR

Zero Cross reference for right channel

0: Zero Cross detector compares positive and negative

inputs

1: Zero Cross detector compares negative input to VMID

ZCSCRL

Zero Cross reference for left channel

0: Zero Cross detector compares positive and negative

inputs

1: Zero Cross detector compares negative input to VMID

R21 (15h)

0010101

ADC Input Mux

LRBOTH

Right Channel Input PGA Controlled by Left Channel Register

0: Right channel uses RAG and MUTERA

1: Right channel uses LAG and MUTELA

WM8590GEDS/RV 데이터시트(PDF) 31 Page - Wolfson Microelectronics plc

WM8590GEDS/RV 데이터시트(HTML) 31 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

데이터시트 다운로드

링크 URL