| 전자부품 데이터시트 검색엔진 |
|
WM8711SEDS/R 데이터시트(PDF) 26 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8711SEDS/R 데이터시트(HTML) 26 Page - Wolfson Microelectronics plc |
|
26 / 47 page ![]() Production Data WM8711 / WM8711L w PD Rev 4.3 September 2006 26 Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC transition, yet MSB is still transmitted first. LEFT CHANNEL RIGHT CHANNEL DACLRC BCLK DACDAT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB Figure 15 Right Justified Mode In DSP/PCM mode, the left channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=1) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |