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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8738GED/V 데이터시트(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8738GED/V 데이터시트(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 18 page  WM8738 Production Data w PD Rev 4.4 August 2006 8 DIGITAL AUDIO INTERFACE TIMING MCLK t MCLKH t MCLKY t MCLKL Figure 1 Master Clock Timing Requirements Test Conditions AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKH 10 ns MCLK System clock pulse width low TMCLKL 10 ns MCLK System clock cycle time TMCLKY 27 ns BCLK LRCLK t BCH t BCL t BCY SDATO t LRS U t LRH t DD Figure 2 Digital Audio Data Timing Test Conditions AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 80 ns BCLK pulse width high tBCH 40 ns BCLK pulse width low tBCL 40 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns SDATO propagation delay from BCLK falling edge tDD 10 ns |
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