WM8746

Production Data

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March 2006, PD Rev 4.0

19

ATTENUATION CONTROL

Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is

0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control

bits. All attenuation registers are double latched allowing new values to be pre-latched to several

channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will

cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation

register is also included, allowing all attenuations to be set to the same value in a single write.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

L0A[7:0]

11111111

(0dB)

Attenuation data for DACL0 in 0.5dB steps, see Table 8.

0000000

Attenuation

DACL0

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACL0 in intermediate latch (no change to output)

1: Store DACL0 and update attenuation on all channels.

7:0

R0A[7:0]

11111111

(0dB)

Attenuation data for DACR0 in 0.5dB steps, see Table 8.

0000001

Attenuation

DACR0

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACR0 in intermediate latch (no change to output)

1: Store DACR0 and update attenuation on all channels.

7:0

L1A[7:0]

11111111

(0dB)

Attenuation data for DACL1 in 0.5dB steps, see Table 8.

0000100

Attenuation

DACL1

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACL1 in intermediate latch (no change to output)

1: Store DACL1 and update attenuation on all channels.

7:0

R1A[7:0]

11111111

(0dB)

Attenuation data for DACR1 in 0.5dB steps, see Table 8.

0000101

Attenuation

DACR1

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACR1 in intermediate latch (no change to output)

1: Store DACR1 and update attenuation on all channels.

7:0

L2A[7:0]

11111111

(0dB)

Attenuation data for DACL2 in 0.5dB steps, see Table 8.

0000110

Attenuation

DACL2

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACL2 in intermediate latch (no change to output)

1: Store DACL2 and update attenuation on all channels.

7:0

R2A[7:0]

11111111

(0dB)

Attenuation data for DACR2 in 0.5dB steps, see Table 8.

0000111

Attenuation

DACR2

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store DACR2 in intermediate latch (no change to output)

1: Store DACR2 and update attenuation on all channels.

7:0

MASTA[7:0]

11111111

(0dB)

Attenuation data for all channels in 0.5dB steps, see Table 8.

0001000

Master

Attenuation

(all channels)

8

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store MASTA[7:0] in all intermediate latches (no change to

output)

1: Store MASTA[7:0] and update attenuation on all channels.

Table 7 Attenuation Register Map

Note:

The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the

relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[7:0]

overwrites any values previously sent to L0A[7:0], L1A[7:0], L2A[7:0], R0A[7:0], R1A[7:0], R2A[7:0].